As the channel lengths of highly integrated MOSFETs decrease, the adverse influences of short-channel effects and source/drain punch-through typically increase. In particular, as the design rules of MOSFETs decrease, leakage currents resulting from short-channel effects typically increase and thereby cause a reduction in refresh time of some memory cells (e.g., DRAM memory cells). To limit these short-channel effects, MOSFETs having recessed channels have been developed. These MOSFETs can include the formation of a recess trench in a semiconductor substrate, which is used to support the formation of an effectively longer channel region even as the lateral dimensions of the MOSFETs within a semiconductor substrate are decreased. The use of effectively longer channel regions may also reduce any need to perform counter doping in a channel region as a means to modify threshold voltage to compensate for short-channel effects.
Conventional methods of forming MOSFETs having recessed channel regions are illustrated by FIGS. 1-4. In particular, FIG. 1 illustrates the formation of oxide-filled trench isolation regions 15, which define a semiconductor active region within a semiconductor substrate 10. A pad oxide layer 20 and a silicon oxynitride layer 25 are formed on a surface of the semiconductor substrate 10. The pad oxide layer 20 and the silicon oxynitride layer 25 collectively define a mask layer 30. A photoresist pattern 35, which may be photolithographically defined using conventional techniques, is formed on the mask layer 30. The spacings “d” between adjacent portions of the photoresist pattern 35 define a width of recess trenches to be formed in the substrate 10 during subsequent process steps. As will be understood by those skilled in the art, photoresist bridging problems may occur as the spacings “d” are reduced in order to achieve higher levels of integration. As illustrated by FIG. 2, the mask layer 30 is then etched using the photoresist pattern 35 as an etching mask. This etching step results in the formation of a pad oxide layer pattern 20a and a silicon oxynitride layer pattern 25a, which collectively define a mask pattern 30a. During this etching step, the surface of the substrate 10 may be exposed. Moreover, because of a reduced selectivity between etching the silicon oxynitride layer 25 and the pad oxide layer 20 relative to the trench isolation regions 15, overetching of the trench isolation regions 15 may occur. This overetching may result in the formation of recesses 40 within the trench isolation regions 15. In some cases, these recesses 40 may expose portions of the substrate 10 which extend along sidewalls of the trench isolation regions 15.
As illustrated by FIG. 3, the photoresist pattern 35 is then removed and followed by the step of selectively etching recess trenches 45 into the substrate 10, using the mask pattern 30a as an etching mask. During this etching step, the recesses 40 within the trench isolation regions 15 may be deepened. FIG. 4 illustrates the removal of the mask pattern 30a using a cleaning step. This cleaning step, which may include exposing the surface of the substrate 10 to chemical etchants (e.g., oxide and polymer residue etchants), may result in a further deepening of the recesses 40 within the trench isolation regions 15. Unfortunately, the formation of relatively deep recesses 40 within the trench isolation regions 15 may result in the exposure of the substrate 10 along sidewalls of the trench isolation regions 15. This exposure of the substrate 10 may support the formation of parasitic transistors and excessive junction leakage within the active region of the substrate 10 and thereby adversely influence the refresh characteristics of memory devices formed in the substrate 10. Thus, notwithstanding conventional methods of forming transistors having recessed channel regions, there continues to be a need for improved methods which are less susceptible to the formation of recesses within trench isolation regions.